I was using a Makefile from the book “Advanced Linux Programming (2001)” [code]. It was strange for me to see that GNU make does compile the code correctly, without even specifying a compiler in the Makefile. It’s like baking without any recipe!
This is a minimal version of the code:
test.c
int main(){}
Makefile
all: test
and make really works! This is the command it executes:
cc test.c -o test
I couldn’t find anything useful in the documentation. How this is possible?
P.S. One additional note: Even the language is not specified; Because test.c is available, GNU make uses cc. If there exists test.cpp or test.cc (when there is no test.c), it uses g++ (and not c++).
Answers:
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Method 1
Make does this using its built-in rules. These tell it in particular how to compile C code and how to link single-object programs.
You actually don’t even need a Makefile:
make test
would work without one.
To see the hidden rules that make all of this possible, use the -p option with no Makefile:
make -p -f /dev/null
The -r option disables these built-in rules.
As pointed out by alephzero, Make has had built-in rules for a very long time (if not always); Stuart Feldman’s first version in Unix V7 defines them in files.c, and his 1979 paper mentions them. They’re also part of the POSIX specification. (This doesn’t mean that all implementations of Make support them — the old Borland Make for DOS doesn’t, at least up to version 3.0.)
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